Instruction-level Real-time Secure Processor Using an Error Correction Code
作者: YOON, S. M.LEE, S. W.PARK, J. K.KIM, J. T.
刊名: Advances in Electrical and Computer Engineering, 2015, Vol.15 (3), pp.13-16
来源数据库: Directory of Open Access Journals
DOI: 10.4316/AECE.2015.03002
关键词: Secure processorSecurityInstructionCorrelationChain
原始语种摘要: In this paper, we present a processor that detects security-attacks at the instruction levelby checking the integrity of instructions in real time. To confirm the integrity of theinstructions, we generate a parity chain of instructions and check them at run time. Theparity chain is generated using an error correction code used in a digital communicationsystem, and the integrity checker has the same function as the error-detector module of theerror correction code. This architecture can readily be applied to a general processor, becausethe checker is located between the processor core and the instruction memory. Compared withother cipher modules with the same key space, our instruction integrity checker achieves afaster check speed and occupies a smaller area.
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  • checker 棋盘式排列
  • integrity 综合性
  • instruction 说瞄
  • processor 处理机
  • detector 探测器检波器
  • correction 校正
  • cipher 密码
  • digital 数字的
  • security 可靠性
  • architecture 构造