Technology mapping for low power in logic synthesis
作者: Vivek TiwariPranav AsharSharad Malik
作者单位: 1Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544, USA
2NEC C&C Research Labs, Princeton, NJ 08540, USA
刊名: Integration, the VLSI Journal, 1996, Vol.20 (3), pp.243-268
来源数据库: Elsevier Journal
DOI: 10.1016/0167-9260(96)00002-8
原始语种摘要: Abstract(#br)Traditionally, three metrics have been used to evaluate the quality of logic circuits - size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of another dimension in the evaluation of circuit quality - its power requirements. Low-power circuits are emerging as an important application domain, and synthesis for low power is demanding attention.(#br)The research presented in this paper addresses one aspect of low-power synthesis. It focuses...
全文获取路径: Elsevier  (合作)
影响因子:0.414 (2012)

  • power 功率
  • mapping 映象
  • synthesis 合成
  • consumption 消耗
  • logic 逻辑
  • technology 工艺
  • difficult 困难的
  • quality 品质
  • level 水准
  • speed 速率