Wojciech M. Zabołotny
||Warsaw Univ. of Technology (Poland)
||Symposium on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments (WILGA)
||SPIE-the International Society for Optical Engineering
The FPGA-implemented data acquisition and processing systems are usually configured via local bus providing access to internal control and status registers. Management of the address space of that local bus is a well known and non-trivial problem, especially in complex hierarchical systems. Even though various solutions have been already proposed, it seems that there is still a need for an open, portable address management system, capable of operation with different local bus technologies and various control interfaces. This paper presents a proposition for such a system. The multi-level hierarchy of nested blocks with internal control and status registers is supported. The blocks and registers may be implemented as single instances or vectors of multiple instances. The structure of the... system is described with the XML file. The generated address map may be stored in various formats compatible with different control interfaces (e.g., IPbus or AXI). The proposed solution is compatible with the design flow based on parametrized high-level HDL implementation of the FPGA firmware.